---------------------------------------------------------------------------------
  -- Design Name : General Purpose Registers
  -- File Name   : IdRegs32_32.vhd
  -- Function    : Contains 32 32b register for general use
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.UserPkg.all;

entity IdRegs32_32 is --treba dodati onaj sluchaj kada je movi
  port (
    clk:      in  std_logic;
    rs1:      in  RegAddr;
    rs2:      in  RegAddr;
    wr:       in  std_logic;
	  cl:       in  std_logic;
    rwr:      in  RegAddr;
	  rwr16:    in  std_logic;
    rwr_data: in  word32;
    rs1_data: out word32;
    rs2_data: out word32
  );
end IdRegs32_32;

architecture behavioral of IdRegs32_32 is
  type t_reg is array(0 to 31) of word32;
  signal regdata : t_reg := (others => "00000000000000000000000000000000");
begin
  rs1_data <= rwr_data when (wr = '1' and rs1 = rwr and rwr16 /= '1') else
              regdata(to_integer(unsigned(rwr)))(LEN_WORD -1 downto 16) & rwr_data(15 downto 0)
                       when (wr = '1' and rs1 = rwr and rwr16  = '1') else
              regdata(to_integer(unsigned(rs1)));

  rs2_data <= rwr_data when (wr = '1' and rs2 = rwr and rwr16 /= '1') else
              regdata(to_integer(unsigned(rwr)))(LEN_WORD -1 downto 16) & rwr_data(15 downto 0)
                       when (wr = '1' and rs2 = rwr and rwr16  = '1') else
              regdata(to_integer(unsigned(rs2)));

  process(clk) is
  begin
    if (falling_edge(clk)) then
      if (cl = '1') then                                                  --clear
        for i in 0 to 31 loop
          regdata(i) <= (others => '0');
        end loop;
      elsif (wr = '1') then                                               --write
        if(rwr16 = '1') then
          regdata(to_integer(unsigned(rwr)))(15 downto 0) <= rwr_data(15 downto 0);
        else
          regdata(to_integer(unsigned(rwr))) <= rwr_data;
        end if;
      end if;
    end if;
  end process;

end architecture behavioral;